A system on chip uses specific algorithms for balancing the data transmission rate between non-real time communication components and those sensitive to delays. The former category can be granted lower priority in network utilization, while the latter needs stricter delay constraints. A system-on-chip’s designers should first analyze the latency requirements of each transaction type.
An integrated circuit (IC) designer should assess the components’ need for continuous data access to the communication network at the system level. Latency tolerance defines the applications’ sensitivity to bandwidth reservation. In terms of computer memory, there is a critical dependence on the memory controller to provide instruction fetching and data transfer. An audio or video processor is used with data processing that is continuous to avoid visual or aural artifacts. In general, there is an imperative for components to continuously access the memory while executing their programs. Thus, each IC designer should use application-specific and system-related requirements per component to classify real-time processes by latency tolerance.
A system on chip (SoC) has latency requirements for communication components that need to consider the allocated segment. Each IC designer should use bandwidth reservation for critical processes, which is adequate to support the given technology’s data transfer rate. For instance, it is essential to reserve the video processor’s traffic bandwidth to ensure that it receives enough memory access during a continuous data processing mode, as this avoids visual artifacts. A similar necessity is applicable to the processor’s continuous video playback to reduce audio interruptions. These examples show that a latency-sensitive component has specific bandwidth requirements during its communication session. Therefore, it is a designer’s responsibility to calculate the communication link’s minimum capacity and ensure that it suits the given component.
There is a need to adjust memory controller arbitration policies to guarantee that a latency-sensitive SoC process has continuous access to memory. The network on chip arbitration setting should be tuned, namely, weighted round-robin, to maintain a steady rate for critical processes and to ensure that other less important transactions have satisfactory memory access bandwidth. An IC designer notes that a high-priority NOC interconnect arbitration setting can result in reduced system utilization. By that, it is prohibited to allow critical transactions to block memory resources since this will deteriorate the overall system performance.
A SoC system’s communication components need arbitration and memory controller policies for maintaining the required capacity. It is essential to consider that a single transaction path, including network segments, can have multiple contention points. The given network segment should be checked for bandwidth requirements to ensure that the component will receive the necessary data transfer rate. A system-level designer should observe each component involved in the given data transmission path to allocate the required memory access bandwidth for it. In this case, there is no need to separately reserve the network bandwidth for each component; instead, the critical processes should provide enough space to avoid contention.
The system performance assessment is necessary for designing a system-on-chip with guaranteed bandwidth to critical components. An IC designer should conduct a series of tests to ensure that the reserved capacity for a latency-sensitive process involves sustained data transmission rate, bandwidth, and memory access level. For the given set of tests, it is beneficial to use an average computational level for typical video conferencing, memory access, and other network transmission rates. There is an added need to include peak data transfer and memory usage rates to observe how the network segment will provide memory access to a component with critical requirements during the given mode and other typical sessions. A system designer should pay specific attention to the sustained rate level to ensure that there is enough capacity allocated to the reserved memory bandwidth. In a similar way, a latency-sensitive application is needed to ensure that it will have continuous memory access during its execution.
Generally, designers can ensure that their system-on-chip (SoC) product has adequate memory allocation for critical components by analyzing application-specific requests and considering the system’s overall performance. It is vital to observe that the system’s memory bandwidth will be sufficient for the selected SoC process. There is a special need to reserve memory access for a latency-sensitive component to ensure that it will provide satisfactory results with continuous data transmission.
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